On Aug 26 2006, 01:44, Jonathan Graham Harston wrote:
> Is there an actual correct explanation for why using 3.5" disk > drives with DFS 1.20 gives "Disk Error 10"? I've given up and just > say "DFS 1.21 works with 3.5" drives by ignores Disk Error 10".
I don't actually know, because all the 3.5" drives I have tried on a Beeb are quite old ones, and do work with an 8271 and DFS 1.20.
"Disk Error 10", meaning "Drive not ready", is a direct result of the /RDY signal becoming inactive on the 8271 during a disk operation. Most drives of the era generate a suitable /READY signal on pin 34, and this can be easily gated with the drive select signals to provide the individual /RDY0 and /RDY1 which the 8271 needs. However, Acorn chose to do it differently, by duplicating what most drives do.
Given that some modern drives do suppress the /INDEX pulse while seeking, I surmise it's to do with fact that the Beeb uses the /INDEX pulse to clock the flip-flops that generate the /RDY signals. If the /RDY signal for the drive in use is high when the 8271 wants to perform an operation on that drive, or becomes high during the command execution, it stops the execution of the command and sets the result register to 1016 which means "operator intervention probably required for recovery; drive not ready".
Each /RDY signal is driven by the /Q output of the second of a pair of D-type flip-flops. These are in IC84 for drive 0, and IC83 for drive 1. Thus when /Q2 is low (ie Q2 is high) the drive is deemed READY.
The RESET input of this flip-flop is driven by the Q output of the first flip-flop, and the SET input of the first flip-flop is driven by the corresponding drive select, so the /RDY signal is disabled until the drive is selected. That is, when the drive select is inactive (high) the first flip-flop is held SET, so Q1 is high, so the second flip-flop is RESET, so Q2 is low and /Q2 is high, ie /RDY is high (not ready). However, once the drive select goes low, this state is no longer enforced, and can be altered according to the state of the flip-flops' data inputs when they get a clock pulse.
The D input to the first of the flip-flops is driven by a signal from a clock divider; this flip-flop's /Q output drives D on the second flip-flop. Both flip-flops are clocked by an inverted INDEX pulse (ie active high rather than active low) from the drive, which normally arrives 5 times a second (the drive runs at 300 rpm), ie at 200ms intervals. This same INDEX clears the clock divider, which makes its output low. The divider consists of IC86 and IC85, and its output is 8MHz divided by 222, or about 1.9Hz. Left to its own devices, the clock divider output would alternate between high and low at about 260ms intervals, ie it would go high about 260ms after the last index pulse, if another didn't arrive fast enough to clear it again.
But these actions aren't instantaneous. In fact the circuit is designed so that some things happen when the first index pulse arrives, some happen on the next one, etc.
Assuming the drive is selected and is up to speed, and has generated a few index pulses, it works as follows:
When another index pulse arrives, the counter gets cleared (again). In this case, its output was already low and the first flip-flop has a low at its D input, which is then clocked by the INDEX pulse, thus making Q1 low and /Q1 high (as it probably was before), so the D input on the second flip-flop is high, and this too is clocked by the INDEX pulse, so Q2 goes high and /Q2 goes low (if it wasn't before), which means the /RDY signal is low (drive is ready).
Initially, however, things are different. Both flip-flops are in the opposite ("not ready") state, and there's a 50/50 chance what state the divider output is in.
Suppose it's high. The first INDEX pulse clears it, but it takes an appreciable time (between 0.5 and 3.5 microseconds) to take effect, by which time the rising edge of that INDEX pulse has already clocked the flip-flops. The first flip-flop "sees" a high input, and the output doesn't change.
The second INDEX pulse once again clears the divider, and this time when the INDEX clocks the first flip-flop, it already had a low on its D input, which is now propagated to Q1; this makes a high on /Q1 which is presented to the D input of the second flip-flop. However, the propagation delay means this arrives after the second flip-flop is clocked, so it still doesn't change state.
When the third INDEX pulse arrives, the divider is cleared again, the first flip-flop remains in its "ready" state, and this time the high state on /Q1 is already there when the second flip-flop is clocked, so finally the 8271 sees a valid /RDY input.
If the divider output were low when the first INDEX pulse arrives, the same process is followed, but one INDEX pulse - one revolution of the disk - earlier.
This is all designed to meet the standard criterion that a drive is "ready" when two consecutive index pulses have been seen at (approximately) the correct interval. If the drive is not yet up to speed and hence the interval is too long, or if one index pulse is missed, the divider will not be cleared, and when the next index pulse arrives, the divider output will be high. Its state will be propagated through the flips-flops such that eventually the drive will appear "not ready".
However, this means that if a drive suppresses an /INDEX pulse during a seek, the effect of that missing pulse is delayed by one or two revolutions of the disk. Thus it is possible for the 8271 to see that the drive is "ready" when it receives the next command (read, write, or seek) but for the drive to apparently become "not ready" during the execution of the command. This would cause the command to be aborted with error 1016.